This work tries to minimize the two objectives chip area and delay in the planning phase with equal attention, resp. it deals with the combination of these two objectives. Therefore it is necessary to describe in detail the three important subareas of floorplanning: placement, global routing, and estimations (of area and delay).
To enable delay minimization the well-known placement method by recursive bipartitioning with terminal propagation is extended in two different ways: On the one hand by classification (into timing critical and uncritical nets as well as into internal and external nets) and on the other hand by budgeting (net length or delay bounds which can lead to binding wishes, a form of weak restrictions).
It was possible to build upon extensive work in the field of area estimation. But for modelling delays a new class of hierarchical timing graphs has been defined and the concept of shape functions has been extended to SD curves (shape and delay curves). During the global routing phase the investigations concentrate on suitable routing graphs and sequential routing procedures which optimize the delays to identified critical sinks.
The results of the theoretical sections of this work find their application in the last chapter which describes some experiments with the PLAYOUT Chip Planner Version 6 that implements selected procedures. It also compares them with an earlier version of the Chip Planner which solely concentrates on area minimization. Because of its modular and object-oriented design the Chip Planner offers an excellent experimentation environment for current and future design technologies in which concepts and ideas can be easily evaluated.
PhD Thesis: Timing-driven Floorplanning beim hierarchischen VLSI-Entwurf
Author: Manfred Schölzke
Committee: Prof. Dr. P. Müller (Supervisor), Prof. Dr. G. Zimmermann (Referee) and Prof. Dr. N. Wehn (Referee)
Date of Scientific Defense: June 18th, 1999
See also Verlag Dr. Kovac - Summary.